1. Field of the Invention
The present invention generally relates to data registers in central processing units and more particularly to using a memory element to expand the available set of data registers.
2. Description of the Related Art
Conventionally, a processor architecture defines the group of operations available to the user (e.g., the instruction set) and the method to access data for these operations (e.g., the register set). The architecture limits data accuracy and range because architected registers store operands and results in a specified number of bits.
An example of limited accuracy is that floating point units implement truncation or rounding to limit the mantissa to the number of bits specified by the architecture. Data range is limited by the architecture because the number of register bits is directly proportional (by a power of 2) to the number of unique values that it can represent.
Therefore, there is a conventional need for a method for the central processing unit (CPU) to operate on registers which are wider than the architected set but which maintain compatibility with the architecture to allow greater data precision and range. Furthermore, there is a conventional need for such a system to be scalable to cover emerging architectures such as Single Instruction Multiple-Data (SIMD).